FPB 1U Clock Divider

... why on earth is reset normalled to the gated clock? This will force the dividers to reset on each clock, rendering the device useless. Shouldn't it be normalled to the gate input?

... why on earth is reset normalled to the gated clock? This will force the dividers to reset on each clock, rendering the device useless. Shouldn't it be normalled to the gate input?
-- jamos

I looked at the webpage. I think you might be mistaken. According to the webpage, the reset is normalled to an AND gate. The AND gate has two independent inputs, an output, and THAT output is normalled to the reset-input.

Let me know if I've misread something from the manufacturer's page.

The gated clock IS the output of the And gate. One and the same. So again this will cause a reset on each transition of the (gated) clock, and no division will occur.

The gated clock IS the output of the And gate. One and the same. So again this will cause a reset on each transition of the (gated) clock, and no division will occur.
-- jamos

"Gated clock" is just the signal in that particular patch example, where they are using the AND to combine a clock signal and a gate signal before patching it to the CLOCK input, instead of letting it go to the RESET via the normal (which is broken by patching RESET to 8)

you would connect something to the reset to break it like another divisor or lfo

The gated clock IS the output of the And gate. One and the same. So again this will cause a reset on each transition of the (gated) clock, and no division will occur.
-- jamos

I think Random is right and you're conflating the patch example with the normalled functionality. The webpage isn't laid out very well.