Thread: FPB 1U Clock Divider
The gated clock IS the output of the And gate. One and the same. So again this will cause a reset on each transition of the (gated) clock, and no division will occur.
The gated clock IS the output of the And gate. One and the same. So again this will cause a reset on each transition of the (gated) clock, and no division will occur.
... why on earth is reset normalled to the gated clock? This will force the dividers to reset on each clock, rendering the device useless. Shouldn't it be normalled to the gate input?