Thread: FPB 1U Clock Divider
... why on earth is reset normalled to the gated clock? This will force the dividers to reset on each clock, rendering the device useless. Shouldn't it be normalled to the gate input?
-- jamos
I looked at the webpage. I think you might be mistaken. According to the webpage, the reset is normalled to an AND gate. The AND gate has two independent inputs, an output, and THAT output is normalled to the reset-input.
Let me know if I've misread something from the manufacturer's page.